A typical semiconductor circuit such as, for example, an integrated logic circuit includes an output node which is driven to high and low states frequently during operation. The node is connected to a reference potential, typically ground, via a logic network comprising a group of logically interconnected transistor switches, and an active element. The network is operative to ground the node responsive to logic inputs thereto when the active element is activated. The node also is connected by means of a load device to a supply voltage for raising the level of the node when the switch is deactivated.
Typically, a passive load is employed in the supply circuit and a current flows through the load when the active element is switched to its on state (accessed). If the load device is passive (an impedance or an unswitched active element), the load must be a weaker conductor than the logic network and the active element, and thus the circuit speed is limited by the conductivity of the load device as is well understood.
An approach which is often used to increase the circuit speed is the use of a high-conductivity active load switched in opposition to the active element. Since the output node is connected to the supply voltage (a high level) by the active load while the circuit is not accessed, the only output transitions which need to be made when the circuit is accessed are high-to-low, which are faster owing to the high conductivity of the logic network and the active element. A disadvantage of the latter circuit is that multistage circuits require separate clocking signals to the individual stages, so that later stages are not activated until earlier stages have completed their high-to-low transitions. Otherwise, false high-to-low transitions of later stages might occur with no mechanism for recovering the desired output. The clocking requirements introduce extra components and result in somewhat slower circuit operation. The problem to which the invention is directed thus is to achieve a multistage circuit in which pull-ups are eliminated from the accessing period without necessitating separate clocking signals to the individual stages.